The present invention relates to an interface apparatus and method for receiving digital data transmitted at any one of a plurality of predetermined transmission rates, and a method and apparatus for identifying the transmission rate of the digital data.
There have been known various systems which handle a signal of a digital transmission format that is transmitted at any one of a plurality of predetermined transmission rates and is in the form of a series of pulses having their respective time lengths or widths (durations) limited within a predetermined range to thereby form patterns of pulse widths peculiar to the signal. Among examples of such systems are high-density recording/reproduction apparatus using the baseband digital modulation scheme to record and reproduce data to and from storage media at a variable rate.
Further, EIAJ (Electronic Industries Association of Japan) Standard CP1201 for use in general-purpose digital audio interfaces has been widely known as an example of an interface system related to such high-density recording/reproduction apparatus. In the field of the digital audio data interfacing, this format is commonly known as the “SPDIF (acronym for Sony, Philips Digital audio Interface)” format and defined in detail in the EIAJ/CP1201 digital audio interface specifications.
In systems using such a transmission format, there would occur no problem in an apparatus that records or transmits signals because the recording or transmitting apparatus itself decides a transmission rate of the signals. However, an apparatus that reproduces or receives the signals would encounter the problem that the reproducing or receiving apparatus can neither apply a phase-locked loop (PLL) nor detect data of each bit unless the transmission rate of the signals is first identified. There have heretofore been known a number of schemes for identifying a signal transmission rate. But, all of the conventionally-known transmission rate identifying schemes are very simple and directed only to counting a length of the peculiar pulse width pattern of the signal using a high-speed clock. As a result, the pulse-width pattern length has to be counted using a considerably high frequency.
In the case of conventional SPDIF signal reception circuits, it has been common to use an analog PLL to generate clock pulses that are in phase with the SPDIF signal and have a frequency corresponding to a multiple of the frequency of the SPDIF signal. Also, there have been proposed and developed various methods and apparatus in relation to the analog-PLL-based SPDIF signal reception circuits and the scheme of locking the PLL. If a sufficiently high frequency is used, similar circuits can be implemented even with a digital PLL.
Although the use of the analog PLL can construct an SPDIF signal reception circuit without using a very high frequency, the greatest concern of a system provided with the SPDIF reception circuit is signal synchronization between the system and the SPDIF reception circuit. If the system is a standalone or independent type based primarily on the SPDIF reception circuit, there would arise no inconvenience. But, in a situation where the SPDIF signal reception is employed as an additional function of an apparatus that processes another type of digital audio signal and when digital mixing is to be performed between the main digital audio signal and the SPDIF signal, the system master clock pulses must be temporarily shifted to reproduce clock pulses produced by an analog PLL locking the SPDIF signal, at which moment there would occur an undesirable interruption in the main digital audio processing.
Typically, where two or more different SPDIF signals are to be received and processed simultaneously, it would be impossible to generate one type of master clock pulse that is synchronous with all of the different SPDIF signals. Thus, in such a situation, digital sampling rate converter circuits are provided in corresponding relation to the different SPDIF signals so that all the input data can be processed with only one type of master clock pulse.
If the received SPDIF signal is merely delivered to another interface for subsequent data transmission to a digital controller, instead of being subjected to audio reproduction, the signal synchronization is no longer the primary concern, but how to communicate the data without data duplication and omission becomes the most important challenge. In this case, it is only necessary that the apparatus provided with the SPDIF signal reception circuit should function as a master apparatus that, whenever data is received, carries out data delivery through a handshake scheme using flags.
In these examples of the SPDIF processing, provision of the analog PLL should be no longer necessary, and there is a great demand for a more sophisticated SPDIF signal reception circuit which can operate stably with low-frequency asynchronous master clock pulses without using the analog PLL and which yet can be of a small circuit size or scale.